1. Field of the Invention
The present invention relates to a wafer burn-in circuit for a semiconductor memory device, and more particularly, to a wafer burn-in circuit for a semiconductor memory device which can detect defected cells in an early stage and increase a yield by applying a stress to bit lines in a wafer state to detect the defected cells and repairing the same.
2. Description of the Related Art
In general, in a conventional burn-in test on a semiconductor memory device, the final test has not been performed in a wafer state due to the high costs, but generally performed in a packaged state by applying a stress to the semiconductor memory device at a long period, using a high voltage (hereinafter, referred to as "burn-in voltage") . According to the conventional burn-in test, as the integrity of the semiconductor memory device to be tested is greater, the test costs thereof increases accordingly. Further, since the repairing can not be performed in the packaged state as mentioned above, the entire yield is deteriorated due to the stress which is occurred during the burn-in test.
In the meantime, in the conventional burn-in test, the yield may be improved by detecting a failure mainly at the word lines in the cells, that is, the gate oxide layer and then repairing them. However, the failures due to the stress in the word lines and the bit lines and the junction stress between the bit lines can not be improved.
In practice, since the burn-in test for the semiconductor memory device is generally performed by enabling the word lines first and alternately varying a high or low level of the cell data applied to the word lines or the bit line junction, while reading and/or writing the cell data from and/or to the cell, the presence of the stress applied to the bit lines is required. However, the conventional burn-in test was a technique which is not able to apply the stress to the bit lines.
Therefore, according to the conventional burn-in test as mentioned above, although the burn-in stress has already been given in the wafer state, since the burn-in test in the packaged state is continuously proceeded, there is a drawback that the advantageous effects of the wafer burn-in test can not be obtained, which results in the difficulty in improving the entire burn-in test time for the semiconductor memory device.